RM0453 Rev 5 241/1450
RM0453 Power control (PWR)
285
When CPU2 is prevented from booting (C2BOOT = 0, boot hold), the wake-up from
low-power mode boot procedure is the following:
• When the system is secure (ESE = 1) and the secure CPU2 boots after reset
(POR/NRST or wake-up from Standby), CPU2 checks the reset source (C2BOOT or
illegal access) in the C2BOOTS bit, as follows:
– C2BOOTS = 1: The secure CPU2 boots from C2BOOT and the normal application
is started.
– C2BOOTS = 0: The secure CPU2 boots due to an illegal access. In this case
CPU2 processes the illegal access and reenters CStop mode. This sets CPU2
back in reset and clears the C2BOOTS flag.
• When waking up from CStop mode, CPU2 checks the wake-up source (C2BOOT or
illegal access) as follows:
– C2BOOTS = 1: The secure CPU2 is re-started by C2BOOT and the normal
application is started. The system is initialized by CPU1. So CPU2 can directly
process the wake-up event
– C2BOOTS = 0: The secure CPU2 restarts due to an illegal access. In this case,
CPU2 processes the illegal access and reenters CStop mode. This sets CPU2
back in CStop mode.
When the system remains in Run mode (due to one CPU), the other CPU wakes up from
CStop mode without the system having gone to a low-power mode.
6.5 Low-power modes
By default, the microcontroller is in Run mode after a system or a power reset and at least
one of the CPUs is in CRun mode executing code. Low-power modes are available to save
power when the CPU does not need to be kept running, for example when it is waiting for an
external event. The user must select the mode giving the best compromise between
consumption, startup time and available wake-up sources.
Each CPU features the following low-power modes, that are entered by the CPU when
executing WFI, WFE or on return from an exception handler when SLEEPONEXIT in the
CPU is enabled:
• CSleep mode: when CPU enters low-power mode and the CPU SLEEPDEEP is
disabled
• CStop mode: when CPU enters low-power mode and the CPU SLEEPDEEP is enabled
These low-power modes are detailed below:
• Sleep mode: CPU clock off, all peripherals including CPU core peripherals (among
them NVIC, SysTick) can run and wake up the CPU when an interrupt or an event
occurs.
• Low-power run mode (LPRun): when the system clock frequency is reduced below
2 MHz. The code is executed from the SRAM or from the flash memory. The regulator
is in low-power mode to minimize the operating current.
• Low-power sleep mode (LPSleep): entered from the LPRun mode.
• Stop 0 mode, and Stop 1 mode: the content of SRAM1, SRAM2 and of all registers is
retained. All clocks in the V
CORE
domain are stopped. PLL, MSI, HSI16 and HSE32 are
disabled. LSI and LSE can be kept running.
RTC can remain active (Stop mode with RTC, Stop mode without RTC). The sub-GHz
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