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STMicroelectronics STM32WL5 Series

STMicroelectronics STM32WL5 Series
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RM0453 Rev 5 1435/1450
RM0453 Debug support (DBG)
1435
Refer to Section 38.13: CPU2 ROM tables for the register boundary addresses.
38.15 References
1. IHI 0031C (ID080813) - Arm
®
Debug Interface Architecture Specification ADIv5.0 to
ADIv5.2, Issue C, 8th Aug 2013
2. DDI 0480F (ID100313) - Arm
®
CoreSight™ SoC-400 r3p2 Technical Reference
Manual, Issue G, 16th March 2015
3. DDI 0461B (ID010111) - Arm
®
CoreSight™ Trace Memory Controller r0p1 Technical
Reference Manual, Issue B, 10 Dec 2010
4. DDI 0314H - Arm
®
CoreSight™ Components Technical Reference Manual, Issue H, 10
July, 2009
5. DDI 0403D (ID100710) - Arm
®
v7-M Architecture Reference Manual, Issue E.b, 2
December 2014
6. DDI 0494-2a (ID062813) - Arm
®
CoreSight™ ETM™-M0+ r0p1 Technical Reference
Manual, Issue D, 6 July, 2015
7. DDI 0440C (ID070610) - Arm
®
CoreSight™ ETM™-M4 r0p1 Technical Reference
Manual, Issue C, 29 June 2012
0xFE8
BPU_PIDR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REVISION
[3:0]
JEDEC
JEP106ID
[6:4]
Reset value 00101011
0xFEC
BPU_PIDR3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REVAND[3:0] CMOD[3:0]
Reset value 00000000
0xFF0
BPU_CIDR0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[7:0]
Reset value 00001101
0xFF4
BPU_CIDR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CLASS[3:0]
PREAMBLE
[11:8]
Reset value 11100000
0xFF8
BPU_CIDR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[19:12]
Reset value 00000101
0xFFC
BPU_CIDR3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[27:20]
Reset value 10110001
Table 287. CPU2 BPU register map and reset values (continued)
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

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