STMicroelectronics STM32WL5 Series User Manual

RM0453 Rev 5 1411/1450
RM0453 Debug support (DBG)
1435
38.12.5 DBGMCU CPU1 APB1 peripheral freeze register 2
(DBGMCU_APB1FZR2)
Address offset: 0x044
Reset value: 0x0000 0000
38.12.6 DBGMCU CPU2 APB1 peripheral freeze register 2
(DBGMCU_C2APB1FZR2)
Address offset: 0x048
Reset value: 0x0000 0000
Bit 0 DBG_TIM2_STOP: TIM2 stop in CPU2 debug
0: Normal operation. TIM2 continues to operate while CPU2 is in debug mode.
1: Stop in debug. TIM2 is frozen while CPU2 is in debug mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_
LPTIM3
_STOP
DBG_
LPTIM2
_STOP
Res. Res. Res. Res. Res.
rw rw
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 DBG_LPTIM3_STOP: LPTIM3 stop in CPU1 debug
0: Normal operation. LPTIM3 continues to operate while CPU1 is in debug mode.
1: Stop in debug. LPTIM3 is frozen while CPU1 is in debug mode.
Bit 5 DBG_LPTIM2_STOP: LPTIM2 stop in CPU1 debug
0: Normal operation. LPTIM2 continues to operate while CPU1 is in debug mode.
1: Stop in debug. LPTIM2 is frozen while CPU1 is in debug mode.
Bits 4:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
151413121110987 6 5 43210
Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_
LPTIM3
_STOP
DBG_
LPTIM2
_STOP
Res. Res. Res. Res. Res.
rw rw
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 DBG_LPTIM3_STOP: LPTIM3 stop in CPU2 debug
0: Normal operation. LPTIM3 continues to operate while CPU2 is in debug mode.
1: Stop in debug. LPTIM3 is frozen while CPU2 is in debug mode.

STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English