RM0453 Rev 5 317/1450
RM0453 Reset and clock control (RCC)
371
7.4.5 RCC clock interrupt enable register (RCC_CIER)
Address offset: 0x018
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
Res. Res. Res. Res. Res. Res.
LSE
CSSIE
Res. Res. Res.
PLL
RDYIE
HSE
RDYIE
HSI
RDYIE
MSI
RDYIE
LSE
RDYIE
LSI
RDYIE
rw rw rw rw rw rw rw
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSIE: LSE clock security system interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the CSS on
LSE.
0: Clock security interrupt caused by LSE clock failure disabled
1: Clock security interrupt caused by LSE clock failure enabled
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYIE: PLL ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 4 HSERDYIE: HSE32 ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the HSE32
oscillator stabilization.
0: HSE32 ready interrupt disabled
1: HSE32 ready interrupt enabled
Bit 3 HSIRDYIE: HSI16 ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the HSI16
oscillator stabilization.
0: HSI16 ready interrupt disabled
1: HSI16 ready interrupt enabled
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