RM0453 Rev 5 281/1450
RM0453 Power control (PWR)
285
Bit 15 C2DS: CPU2 Deep-Sleep mode
This bit is set by hardware when CPU2 enters Deep-Sleep mode or is hold by C2BOOT.
0: CPU2 running or in sleep
1: CPU2 in Deep-Sleep or hold by C2BOOT
Bit 14 C1DS: CPU1 Deep-Sleep mode
This bit is set by hardware when CPU1 enters Deep-Sleep mode.
0: CPU1 is running or in sleep
1: CPU1 is in Deep-Sleep
Bit 13 C2STOPF: System Stop 0, 1 flag for CPU2 (all core states retained)
This bit is set by hardware and cleared only by any reset or by setting C2CSSF bit.
0: System has not been in Stop 0 or 1 mode.
1: System has been in Stop 0 or 1 mode.
Bit 12 C2STOP2F: System Stop 2 flag for CPU2 (partial core states retained)
This bit is set by hardware and cleared only by any reset or by setting C2CSSF bit.
0: System has not been in Stop 2 mode.
1: System has been in Stop 2 mode.
Bit 11 C2SBF: System Standby flag for CPU2 (no core states retained)
This bit is set by hardware and cleared only by a POR reset or by setting C2CSSF bit.
0: System has not been in Standby mode.
1: System has been in Standby mode.
Bit 10 C1STOPF: System Stop 0, 1 flag for CPU1 (all core states retained)
This bit is set by hardware and cleared only by any reset or by setting C1CSSF bit.
0: System has not been in Stop 0 or 1 mode
1: System has been in Stop 0 or 1 mode.
Bit 9 C1STOP2F: System Stop 2 flag for CPU1 (partial core states retained)
This bit is set by hardware and cleared only by any reset or by setting C1CSSF bit.
0: System has not been in Stop 2 mode
1: System has been in Stop 2 mode.
Bit 8 C1SBF: System Standby flag for CPU1 (no core states retained)
This bit is set by hardware and cleared only by a POR reset or by setting C1CSSF bit.
0: System has not been in Standby mode
1: System has been in Standby mode.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 C2CSSF: Clear CPU2 Stop Standby flags
Setting this bit clears the C2STOPF and C2SBF bits.
Bit 0 C1CSSF: Clear CPU1 Stop Standby flags
Setting this bit clears the C1STOPF and C1SBF bits.
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