RM0453 Rev 5 1205/1450
RM0453 Low-power universal asynchronous receiver transmitter (LPUART)
1253
36.4.2 LPUART signals
LPUART bidirectional communications requires a minimum of two pins: Receive Data In
(RX) and Transmit Data Out (TX):
• RX (Receive Data Input)
RX is the serial data input.
• TX (Transmit Data Output)
When the transmitter is disabled, the output pin returns to its I/O port configuration.
When the transmitter is enabled and nothing is to be transmitted, the TX pin is at high
level. In Single-wire mode, this I/O is used to transmit and receive the data.
RS232 hardware flow control mode
The following pins are required in RS232 Hardware flow control mode:
• CTS (Clear To Send)
When driven high, this signal blocks the data transmission at the end of the current
transfer.
• RTS (Request to send)
When it is low, this signal indicates that the USART is ready to receive data.
RS485 hardware flow control mode
The following pin is required in RS485 Hardware control mode:
• DE (Driver Enable)
This signal activates the transmission mode of the external transceiver.
Note: DE and RTS share the same pin.
36.4.3 LPUART character description
The word length can be set to 7 or 8 or 9 bits, by programming the M bits (M0: bit 12 and
M1: bit 28) in the LPUART_CR1 register (see Figure 307).
• 7-bit character length: M[1:0] = ‘10’
• 8-bit character length: M[1:0] = ‘00’
• 9-bit character length: M[1:0] = ‘01’
By default, the signal (TX or RX) is in low state during the start bit. It is in high state during
the stop bit.
These values can be inverted, separately for each signal, through polarity configuration
control.
An Idle character is interpreted as an entire frame of “1”s. (The number of “1” ‘s includes
the number of stop bits).
A Break character is interpreted on receiving “0”s for a frame period. At the end of the
break frame, the transmitter inserts 2 stop bits.
Transmission and reception are driven by a common baud rate generator. The transmission
and reception clocks are generated when the enable bit is set for the transmitter and
receiver, respectively.
The details of each block is given below.
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