Power control (PWR) RM0453
260/1450 RM0453 Rev 5
I/O states in Standby mode
In Standby mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx
registers (x = A, B, C, H)), or with a pull-down (refer to PWR_PDCRx registers (x = A, B, C,
H)), or can be kept in analog state.
The RTC output on PC13 only is functional in Standby mode. PC14 and PC15 used for LSE
are also functional. Three wake-up pins (WKUPx, x = 1, 2, 3) and the three TAMP tampers
are available.
The sub-GHz radio is functional and PVD can be enabled.
Enter Standby mode
The Standby mode is entered according Section 6.5.3, when the SLEEPDEEP bit in the
Cortex system control register is set (see Table 54 for details).
In Standby mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 30.3: IWDG functional description.
• Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain
control register (RCC_BDCR)
• Internal RC oscillator (LSI): this is configured by the LSIxON bit in the control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the backup
domain control register (RCC_BDCR)
• Sub-GHz radio activity, as programmed, see Section 5: Sub-GHz radio (SUBGHZ).
• PVD detection configured in PWR control register 3 (PWR_CR3).
Exit Standby mode
The Standby mode is exited according to Section 6.5.4. The SBF status flags (CnSBF) in
the PWR extended status and status clear register (PWR_EXTSCR) indicate that the MCU
was in Standby mode. All registers are reset after wake-up from Standby except for PWR
extended status and status clear register (PWR_EXTSCR).
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