RM0453 Rev 5 289/1450
RM0453 Reset and clock control (RCC)
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Most peripheral clocks are derived from their bus clock (HCLK, PCLK) except the following:
• The clock used for true RNG, is derived (selected by software) from one of the following
sources:
– PLL VCO (PLLQCLK) (only available in Run mode)
– MSI (only available in Run mode)
– LSI clock
– LSE clock
• The ADC clock is derived (selected by software) from one of the following sources:
– system clock (SYSCLK) (only available in Run mode)
– HSI16 clock (only available in Run mode)
– PLL VCO (PLLPCLK) (only available in Run mode)
• The DAC uses the LSI clock in sample and hold mode
• The (LP)U(S)ARTs clocks are derived (selected by software) from one of the following
sources:
– system clock (SYSCLK) (only available in Run mode)
– HSI16 clock (available in Run and Stop modes)
– LSE clock (available in Run and Stop modes)
– APB clock (PCLK depending on which APB the U(S)ART is mapped) (available in
CRun and CSleep when also enabled in (LP)U(S)ARTxSMEN.)
The wake-up from Stop mode is supported only when the clock is HSI16 or LSE.
• The I2Cs clocks are derived (selected by software) from one of the following sources:
– system clock (SYSCLK) (only available in Run mode)
– HSI16 clock (available in Run and Stop modes)
– APB clock (PCLK depending on which APB the I2C is mapped) (available in CRun
and CSleep when also enabled in I2CxSMEN.)
The wake-up from Stop mode is supported only when the clock is HSI16.
• The SPI2S2 I2S clock is derived (selected by software) from one of the following
sources:
– HSI16 clock (only available in Run mode)
– PLL VCO (PLLQCLK) (only available in Run mode)
– external input I2S_CK (available in Run and Stop modes)
– The SPI2S2 clock in SPI mode is provided by PCLK1 clock.
– I2S mode is selected through register SPIx_I2SCFGR I2SMOD field
• The low-power timers (LPTIMx) clock is derived (selected by software) from one of the
following sources:
– LSI clock (available in Run and Stop modes)
– LSE clock (available in Run and Stop modes)
– HSI16 clock (only available in Run mode)
– APB clock (PCLK depending on which APB the LPTIMx is mapped) (available in
Run and CStop when enabled in LPTIMxSMEN.)
– external clock mapped on LPTIMx_IN1 (available in Run and Stop modes)
The functionality in Stop mode (including wake-up) is supported only when the clock is
LSI or LSE, or in external clock mode.