RM0453 Rev 5 405/1450
RM0453 General-purpose I/Os (GPIO)
431
To each bit in GPIOx_ODR correspond two control bits in GPIOx_BSRR, BS(i) and BR(i):
• When written to 1, BS(i) sets the corresponding ODR(i) bit.
• When written to 1, BR(i) resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using GPIOx_BSRR to change the values of individual bits in GPIOx_ODR is a “one-shot”
effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be
accessed directly. GPIOx_BSRR provides a way of performing atomic bitwise handling.
There is no software need to disable interrupts when programming GPIOx_ODR at bit level:
it is possible to modify one or more bits in a single atomic AHB write access.
10.3.6 GPIO locking mechanism
It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. Frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write GPIOx_LCKR, a specific write/read sequence must be applied. When the right
LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock
the I/Os configuration (during the write sequence, LCKR[15:0] value must be the same).
When the LOCK sequence is applied to a port bit, the value of the port bit can no longer be
modified until the next MCU reset or peripheral reset.
Each GPIOx_LCKR bit freezes the corresponding bit in the control registers
GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL
and GPIOx_AFRH.
The LOCK sequence can only be performed using a word (32-bit long) access to
GPIOx_LCKR due to the fact that GPIOx_LCKR bit 16 must be set at the same time as the
[15:0] bits.
10.3.7 I/O alternate function input/output
Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O: GPIOx_AFRL and GPIOx_AFRH.
With these registers, the user can connect an alternate function to some other pin as
required by the application. This means that a number of possible peripheral functions are
multiplexed on each GPIO. The application can thus select any one of the possible functions
for each I/O.
The AF selection signal being common to the alternate function input and alternate function
output, a single channel is selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin, refer to the product datasheet.
10.3.8 External interrupt/wake-up lines
All ports have external interrupt capability.
To use external interrupt lines, the port must be configured in input mode.
Refer to Section 16.4.1: EXTI configurable event input wake-up.
To Next Page
Loading...
Need help?
General
