STMicroelectronics STM32WL5 Series - Page 473

RM0453 Rev 5 473/1450
RM0453 Direct memory access controller (DMA)
479
Bits 11:10 MSIZE[1:0]: Memory size
Defines the data size of each DMA transfer to the identified memory.
In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and
the peripheral destination if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
Note: This bitfield is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 9:8 PSIZE[1:0]: Peripheral size
Defines the data size of each DMA transfer to the identified peripheral.
In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1
and the peripheral source if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
Note: This bitfield is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 7 MINC: Memory increment mode
Defines the increment mode for each DMA transfer to the identified memory.
In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory
destination if DIR = 0.
In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).