Extended interrupts and event controller (EXTI) RM0453
522/1450 RM0453 Rev 5
16.6.11 EXTI interrupt mask register (EXTI_CnIMR2)
Address offset: Block 1: 0x090
Address offset: Block 2: 0x0D0
Reset value: 0x0000 0000
16.6.12 EXTI event mask register (EXTI_CnEMR2)
Address offset: Block 1: 0x094
Address offset: Block 2: 0x0D4
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. IM46 IM45 IM44 IM43 IM42 IM41 IM40 IM39 IM38 IM37 IM36 Res. IM34 Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 IM46: Wake-up with interrupt mask on event input 46
0: Wake-up with interrupt request from line 46 is masked.
1: Wake-up with interrupt request from line 46 is unmasked.
Bit 13 IM45: Wake-up with interrupt mask on event input 45
Bit 12 IM44: Wake-up with interrupt mask on event input 44
Bit 11 IM43: Wake-up with interrupt mask on event input 43
Bit 10 IM42: Wake-up with interrupt mask on event input 42
Bit 9 IM41: Wake-up with interrupt mask on event input 41
Bit 8 IM40: Wake-up with interrupt mask on event input 40
Bit 7 IM39: Wake-up with interrupt mask on event input 39
Bit 6 IM38: Wake-up with interrupt mask on event input 38
Bit 5 IM37: Wake-up with interrupt mask on event input 37
Bit 4 IM36: Wake-up with interrupt mask on event input 36
Bit 3 Reserved, must be kept at reset value.
Bit 2 IM34: Wake-up with interrupt mask on event input 34
Bits 1:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. EM41 EM40 Res. Res. Res. Res. Res. Res. Res. Res.
rw rw
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