RM0453 Rev 5 611/1450
RM0453 Digital-to-analog converter (DAC)
616
19.7.6 DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
19.7.7 DAC status register (DAC_SR)
Address offset: 0x34
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. DACC1DOR[11:0]
rrrrrrrrrrrr
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
BWST1
CAL_
FLAG1
DMAU
DR1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rrrc_w1
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 BWST1: DAC channel1 busy writing sample time flag
This bit is systematically set just after Sample and hold mode enable and is set each time the
software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of
DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization).
0:There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1:There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
Bit 14 CAL_FLAG1: DAC channel1 calibration offset status
This bit is set and cleared by hardware
0: calibration trimming value is lower than the offset correction value
1: calibration trimming value is equal or greater than the offset correction value
Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel1
1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
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