True random number generator (RNG) RM0453
640/1450 RM0453 Rev 5
Note: The clock error has no impact on generated random numbers that is the application can still
read the RNG_DR register.
CEIS is set only when CECS is set to 1 by RNG.
Noise source error detection
When a noise source (or seed) error occurs, the RNG stops generating random numbers
and sets to 1 both SEIS and SECS bits to indicate that a seed error occurred. If a value is
available in the RNG_DR register, it must not be used as it may not have enough entropy.
The following sequence must be used to fully recover from a seed error:
1. Software reset by writing CONDRST at 1 and at 0 (see bitfield description for details).
In this case application must clear the SEIS bit interrupt flag.
2. wait for CONDRST to be cleared in the RNG_CR register, then confirm that SEIS is
cleared in the RNG_SR register.
3. wait for SECS to be cleared by RNG. The random number generation is now back to
normal.
22.3.8 RNG low-power use
If power consumption is a concern, the RNG can be disabled as soon as the DRDY bit is set
to 1 by setting the RNGEN bit to 0 in the RNG_CR register. As the post-processing logic and
the output buffer remain operational while RNGEN = 0 following features are available to
the software:
• If there are valid words in the output buffer four random numbers can still be read from
the RNG_DR register.
• If there are valid bits in the conditioning output internal register four additional random
numbers can be still be read from the RNG_DR register. If it is not the case RNG must
be reenabled by the application until the expected new noise source bits threshold is
reached (128-bit in NIST mode) and a complete conditioning round is done.
Four new random words are then available only if the expected number of conditioning
round is reached (two if NISTC = 0). The overall time can be found in Section 22.5:
RNG processing time on page 641.
When disabling the RNG the user deactivates all the analog seed generators, whose power
consumption is given in the datasheet electrical characteristics section. The user also gates
all the logic clocked by the RNG clock. Note that this strategy is adding latency before a
random sample is available on the RNG_DR register, because of the RNG initialization time.
If the RNG block is disabled during initialization (that is well before the DRDY bit rises for the
first time), the initialization sequence resumes from where it was stopped when RNGEN bit
is set to 1, unless the application resets the conditioning logic using CONDRST bit in the
RNG_CR register.
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