AMD K5

Signal Overview 5-3
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Figure 5-1. Signal Groups
A20M
A31–A3
AP
ADS
ADSC
APCHK
BE7–BE0
AHOLD
BOFF
BREQ
HLDA
HOLD
D/C
EWBE
LOCK
M/IO
NA
SCYC
W/R
CACHE
KEN
PCD
PWT
WB/WT
Clock
Bus
Arbitration
CLK
BF
FRCMC IERR TCK TDI TDO TMS TRST
BRDY
BRDYC
D63–D0
DP7–DP0
PCHK
PEN
EADS
HIT
HITM
INV
FERR
IGNNE
BUSCHK
FLUSH
INIT
INTR
NMI
PRDY
R/S
RESET
SMI
SMIACT
STPCLK
Test and Debug
Data
and
Data
Parity
Inquire
Cycles
Floating-Point
Errors
External
Interrupts,
Interrupt
Acknowledge,
and Reset
Address
and
Address
Parity
Cycle
Definition
and
Control
Cache
Control
AMD-K5
Processor
(BF1–BF0)