AMD K5

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AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
EFLAGS.IF—The IF bit in the EFLAGS register
CS:EIP—A logical address, expressed as a segment selector (CS) and offset (EIP)
000F_FFF0h—A physical-memory address using hexadecimal notation
Terminology
The following definitions apply throughout this document:
■ Pin and Signal—A pin is a piece of metal on the processor’s package. A signal is
the information about logical states that a pin carries. Pins have pin numbers; sig-
nals have signal names. On processors that multiplex signals, pins can carry more
than one signal; the AMD-K5 processor, however, does not multiplex signals in
this manner.
■ Assert and Negate—A signal that is driven or sampled active is asserted. A signal
that is inactive is negated. In general, asserted means sampled asserted either by
the processor or target logic. Signals that are active in a Low-voltage state, such as
BRDY, are shown with an overbar. Signals that are active in a High-voltage state,
such as INTR, are shown without an overbar. Dual-state signals, such as R/S and
WB/WT, have two states of assertion and, therefore, the term asserted has no
meaning; such dual-state signals are driven High or Low.
■ Drive and Sample—A single-state signal is driven when it is asserted or negated by
a logic device; it is sampled when its driven state is detected by another device.
■ Cycle and Clock—This term commonly refers to at least four different things:
• Bus-clock period: The cycle time of the CLK signal.
• Processor-clock period: The cycle time of the processor’s internal clock, which
has a frequency relative to CLK that is determined by the state of the BF sig-
nal(s) during RESET. Whenever this cycle is meant, such as in the Chapter 4
description of pipeline timing and the instruction latency, the full name, pro-
cessor-clock cycle, is used.
• Bus cycle: A signal protocol on the processor’s bus, such as a single-transfer
read cycle or a special bus cycle.
• Sequence of bus cycles: One or more contiguous bus cycles. For example, the two
bus cycles that constitute an interrupt acknowledgment are called a bus opera-
tion, so that the constituent bus cycles can be distinguished from the entire op-
eration.