AMD K5

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18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
■ Writeback—This term refers to two related concepts:
• Bus Cycle—A 32-byte burst write cycle to a memory block that has been cached
in the modified state. Writebacks can be caused by inquire cycles, internal
snoops, writeback and invalidate operations (such as FLUSH or the WBINVD
instruction), cache-line replacements, or locked operations on cached loca-
tions. It is sometimes called a copyback.
• Cache-Line State—A cache line in the modified or exclusive MESI state (modi-
fied, exclusive, shared, invalid).
■ Writethrough—This term refers to two related concepts:
• Bus Cycle—A 1-to-8-byte, single-transfer write cycle caused by write misses or
write hits to lines in the shared or exclusive MESI state.
• Cache-Line State—A cache line in the shared MESI state.
■ Flush—This term commonly refers to at least four things and is usually avoided in
favor of the following specific terms:
• Pipeline Invalidation: A pipeline-flush operation invalidates instructions in the
pipeline that have not been retired (and, depending on the type of pipeline in-
validation, entries in the reorder buffer, entries in the TLB, and/or branch-pre-
diction bits) without writing their state to any storage resource.
• Cache Invalidation: The INVD instruction invalidates the contents of the in-
struction and data caches, without writing modified data back to memory.
• Cache Writeback and Invalidation: The WBINVD instruction writes modified
lines in the data cache back to memory while invalidating each line in the in-
struction and data caches.
• FLUSH Operation: The FLUSH input signal executes the same microcode rou-
tine as the WBINVD instruction to write modified lines in the data cache back
to memory while invalidating each line in the instruction and data caches.
■ Flush Acknowledge Cycle—This term commonly refers to different types of special
bus cycles driven by the processor, and is therefore avoided in favor of the follow-
ing specific terms:
• FLUSH Acknowledge: A special bus cycle driven after the FLUSH operation
completes.
• INVD Acknowledge: A special bus cycle driven after the INVD cache invalida-
tion completes.
• WBINVD Acknowledge: A sequence of two special bus cycles driven after the
WBINVD cache writeback and invalidation completes.
■ Snoop—This term commonly refers to at least three different actions and is there-
fore avoided in favor of the following specific terms:
• Inquire Cycles: These are bus cycles driven by system logic. They cause the pro-
cessor to compare the inquire-cycle address with the processor’s physical