5-48 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
BUSCHK is asserted and recognizes latched interrupts in prior-
ity order when BUSCHK is negated.
The MCE bit in CR4, which enables machine check exceptions
during BUSCHK, also enables machine check exceptions dur-
ing data parity errors that are indicated on PCHK while PEN is
asserted.
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