5-142 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
BRDY, the processor latches the physical address and cycle
definition of the failed bus cycle in its 64-bit machine-check
address register (MCAR) and its 64-bit machine-check type
register (MCTR). For details on such parity errors, see the
descriptions of PCHK and PEN on pages 5-101 and 5-102.
While Figure 5-2 shows BRDY returned in the next clock after
ADS, most DRAM-based systems add wait states (idle clocks)
between ADS and BRDY.
To Next Page
Loading...
