Memory Management Unit (MMU) 2-29
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
the TLB reload involves a write to memory to set the PDE
Accessed or Dirty bit, a hit during the physical-tag snoop
causes the cache line to be invalidated.
Details on software configuration for 4-Mbyte paging are given
in Section 3.1.2 on page 3-5. The global-page option is
described in Section 3.1.3 on page 3-9. Details on the TLB stor-
age formats and their testing are given in Section 7.4 on page
7-7.
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