AMD K5 User Manual

Memory Management Unit (MMU) 2-29
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
the TLB reload involves a write to memory to set the PDE
Accessed or Dirty bit, a hit during the physical-tag snoop
causes the cache line to be invalidated.
Details on software configuration for 4-Mbyte paging are given
in Section 3.1.2 on page 3-5. The global-page option is
described in Section 3.1.3 on page 3-9. Details on the TLB stor-
age formats and their testing are given in Section 7.4 on page
7-7.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm