AMD K5

ix
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Appendix A Compatibility With the Pentium and 486 Processors A-1
A.1 Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.1.1 Signal Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.2 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A.2.1 Updates to Descriptor Accessed and TSS Busy Bits . . . . . . . A-5
A.2.2 Locked and Unlocked CMPXCHG8B Operation . . . . . . . . . . A-5
A.2.3 Bus Cycle Order of Misaligned Memory and I/O Cycles . . . . A-6
A.2.4 Halt Cycle after FLUSH
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
A.2.5 Selectable Drive Strengths on Output Driver . . . . . . . . . . . . A-6
Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
A.3 Bus Mastering Operations (including Snooping) . . . . . . . . . . A-8
A.3.1 AHOLD Snoop to Linefill Buffer Prior to or Coincident
with the Establishment of the Cacheability of the Line . . . . A-8
Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
A.3.2 BOFF
Asserted before Snoop to Linefill Buffer and
after the Cacheability of the Line is Established . . . . . . . . . . A-8
Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
A.3.3 Snoop Before Write Hit to ICACHE Appears on Bus . . . . . . A-9
A.3.4 Invalidations during a FLUSH
/WBINVD . . . . . . . . . . . . . . . . A-9
A.3.5 Cache Line Ownership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
A.3.6 Write Hit to a Shared Line in the DCACHE . . . . . . . . . . . . . A-10
A.4 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
A.4.1 Speculative TLB Refills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
A.4.2 Page Fault Encountered by a Load/Store
Type of Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
A.5 Power Saving Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12
A.5.1 STPCLK in Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12
A.5.2 STPCLK
Pulse does not Guarantee That
One Instruction Executes . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12
A.5.3 Simultaneous I/O SMI
Trap and Debug Breakpoint Trap . . A-12
A.5.4 SMM Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
A.5.5 NMI Recognition during SMM . . . . . . . . . . . . . . . . . . . . . . . . A-13
Comment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
A.6 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14
A.6.1 Limit Faults on an Invalid Instruction . . . . . . . . . . . . . . . . . A-14
A.6.2 Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14
A.7 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
A.7.1 Proprietary Branch Trace Messages . . . . . . . . . . . . . . . . . . . A-15
A.7.2 Multiple Debug Breakpoint Matches . . . . . . . . . . . . . . . . . . A-15
A.7.3 Simultaneous Debug Trap and Debug Fault . . . . . . . . . . . . A-15