Real-time clock (RTC) RM0453
1026/1450 RM0453 Rev 5
32.6.18 RTC status register (RTC_SR)
Address offset: 0x50
Backup domain reset value: 0x0000 0000
System reset: not affected
Note: The bits of this register are cleared 2 APB clock cycles after setting their corresponding
clear bit in the RTC_SCR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res.
SSR
UF
ITSF TSOVF TSF WUTF ALRBF ALRAF
rrrrrrr
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 SSRUF: SSR underflow flag
This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1.
Bit 5 ITSF: Internal timestamp flag
This flag is set by hardware when a timestamp on the internal event occurs.
Bit 4 TSOVF: Timestamp overflow flag
This flag is set by hardware when a timestamp event occurs while TSF is already set.
It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise,
an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit
is cleared.
Bit 3 TSF: Timestamp flag
This flag is set by hardware when a timestamp event occurs.
If ITSF flag is set, TSF must be cleared together with ITSF.
Bit 2 WUTF: Wake-up timer flag
This flag is set by hardware when the wake-up auto-reload counter reaches 0.
If WUTOCLR[15:0] is different from 0x0000, WUTF is cleared by hardware when the wake-
up auto-reload counter reaches WUTOCLR value.
If WUTOCLR[15:0] is 0x0000, WUTF must be cleared by software.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1
again.
Bit 1 ALRBF: Alarm B flag
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
alarm B register (RTC_ALRMBR).
Bit 0 ALRAF: Alarm A flag
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
alarm A register (RTC_ALRMAR).
To Next Page
Loading...
Need help?
General
