STMicroelectronics STM32WL5 Series - Page 1043

RM0453 Rev 5 1043/1450
RM0453 Tamper and backup registers (TAMP)
1048
33.6.6 TAMP status register (TAMP_SR)
Address offset: 0x30
Backup domain reset value: 0x0000 0000
System reset: not affected
Bit 21 ITAMP6IE: Internal tamper 6 interrupt enable
0: Internal tamper 6 interrupt disabled.
1: Internal tamper 6 interrupt enabled.
Bit 20 ITAMP5IE: Internal tamper 5 interrupt enable
0: Internal tamper 5 interrupt disabled.
1: Internal tamper 5 interrupt enabled.
Bit 19 Reserved, must be kept at reset value.
Bit 18 ITAMP3IE: Internal tamper 3 interrupt enable
0: Internal tamper 3 interrupt disabled.
1: Internal tamper 3 interrupt enabled.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3IE: Tamper 3 interrupt enable
0: Tamper 3 interrupt disabled.
1: Tamper 3 interrupt enabled..
Bit 1 TAMP2IE: Tamper 2 interrupt enable
0: Tamper 2 interrupt disabled.
1: Tamper 2 interrupt enabled.
Bit 0 TAMP1IE: Tamper 1 interrupt enable
0: Tamper 1 interrupt disabled.
1: Tamper 1 interrupt enabled.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res.
ITAMP8
F
Res.
ITAMP6
F
ITAMP5
F
Res.
ITAMP3
F
Res. Res.
rrrr
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TAMP
3F
TAMP
2F
TAMP
1F
r
rr
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 ITAMP8F: Internal tamper 8 flag
This flag is set by hardware when a tamper detection event is detected on the internal
tamper 8.
Bit 22 Reserved, must be kept at reset value.