Inter-integrated circuit (I2C) interface RM0453
1108/1450 RM0453 Rev 5
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:17 ADDCODE[6:0]: Address match code (slave mode)
These bits are updated with the received address when an address match event occurs
(ADDR = 1).
In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the two
MSBs of the address.
Bit 16 DIR: Transfer direction (slave mode)
This flag is updated when an address match event occurs (ADDR = 1).
0: Write transfer, slave enters receiver mode.
1: Read transfer, slave enters transmitter mode.
Bit 15 BUSY: Bus busy
This flag indicates that a communication is in progress on the bus. It is set by hardware
when a START condition is detected. It is cleared by hardware when a STOP condition is
detected, or when PE = 0.
Bit 14 Reserved, must be kept at reset value.
Bit 13 ALERT: SMBus alert
This flag is set by hardware when SMBHEN = 1 (SMBus host configuration), ALERTEN = 1
and an SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software
by setting the ALERTCF bit.
Note: This bit is cleared by hardware when PE = 0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 34.3.
Bit 12 TIMEOUT: Timeout or t
LOW
detection flag
This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared
by software by setting the TIMEOUTCF bit.
Note: This bit is cleared by hardware when PE = 0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 34.3.
Bit 11 PECERR: PEC Error in reception
This flag is set by hardware when the received PEC does not match with the PEC register
content. A NACK is automatically sent after the wrong PEC reception. It is cleared by
software by setting the PECCF bit.
Note: This bit is cleared by hardware when PE = 0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 34.3.
Bit 10 OVR: Overrun/Underrun (slave mode)
This flag is set by hardware in slave mode with NOSTRETCH = 1, when an
overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 9 ARLO: Arbitration lost
This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the
ARLOCF bit.
Note: This bit is cleared by hardware when PE = 0.
To Next Page
Loading...
Need help?
General
