STMicroelectronics STM32WL5 Series - Page 1107

RM0453 Rev 5 1107/1450
RM0453 Inter-integrated circuit (I2C) interface
1113
Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to
“0x00000000”.
Refer to Section 34.3.
34.7.7 I2C interrupt and status register (I2C_ISR)
Address offset: 0x18
Reset value: 0x0000 0001
Access: No wait states
Bit 31 TEXTEN: Extended clock timeout enable
0: Extended clock timeout detection is disabled
1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more
than t
LOW:EXT
is done by the I2C interface, a timeout error is detected (TIMEOUT = 1).
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 TIMEOUTB[11:0]: Bus timeout B
This field is used to configure the cumulative clock extension timeout:
In master mode, the master cumulative clock low extend time (t
LOW:MEXT
) is detected
In slave mode, the slave cumulative clock low extend time (t
LOW:SEXT
) is detected
t
LOW:EXT
= (TIMEOUTB + TIDLE = 01) x 2048 x t
I2CCLK
Note: These bits can be written only when TEXTEN = 0.
Bit 15 TIMOUTEN: Clock timeout enable
0: SCL timeout detection is disabled
1: SCL timeout detection is enabled: when SCL is low for more than t
TIMEOUT
(TIDLE = 0) or
high for more than t
IDLE
(TIDLE = 1), a timeout error is detected (TIMEOUT = 1).
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 TIDLE: Idle clock timeout detection
0: TIMEOUTA is used to detect SCL low timeout
1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Note: This bit can be written only when TIMOUTEN = 0.
Bits 11:0 TIMEOUTA[11:0]: Bus Timeout A
This field is used to configure:
The SCL low timeout condition t
TIMEOUT
when TIDLE = 0
t
TIMEOUT
= (TIMEOUTA + 1) x 2048 x t
I2CCLK
The bus idle condition (both SCL and SDA high) when TIDLE = 1
t
IDLE
= (TIMEOUTA + 1) x 4 x t
I2CCLK
Note: These bits can be written only when TIMOUTEN = 0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] DIR
rrrrrrrr
1514131211109876543210
BUSY Res. ALERT
TIME
OUT
PEC
ERR
OVR ARLO BERR TCR TC STOPF NACKF ADDR RXNE TXIS TXE
r rrrrrrrrrrrrrsrs