EasyManuals Logo

STMicroelectronics STM32WL5 Series User Manual

STMicroelectronics STM32WL5 Series
1450 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #1195 background imageLoading...
Page #1195 background image
RM0453 Rev 5 1195/1450
RM0453 Universal synchronous/asynchronous receiver transmitter (USART/UART)
1253
35.8.11 USART interrupt flag clear register (USART_ICR)
Address offset: 0x20
Reset value: 0x0000 0000
Bit 2 NE: Noise detection flag
This bit is set by hardware when noise is detected on a received frame. It is cleared by
software, writing 1 to the NECF bit in the USART_ICR register.
0: No noise is detected
1: Noise is detected
Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit
which itself generates an interrupt. An interrupt is generated when the NE flag is set
during multi buffer communication if the EIE bit is set.
When the line is noise-free, the NE flag can be disabled by programming the ONEBIT
bit to 1 to increase the USART tolerance to deviations (Refer to Section 35.5.8:
Tolerance of the USART receiver to clock deviation on page 1133).
Bit 1 FE: Framing error
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register.
When transmitting data in Smartcard mode, this bit is set when the maximum number of
transmit attempts is reached without success (the card NACKs the data frame).
An interrupt is generated if EIE = 1 in the USART_CR3 register.
0: No Framing error is detected
1: Framing error or break character is detected
Bit 0 PE: Parity error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
software, writing 1 to the PECF in the USART_ICR register.
An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0: No parity error
1: Parity error
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WUCF Res. Res. CMCF Res.
ww
1514131211109876543210
Res. Res. UDRCF EOBCF RTOCF Res. CTSCF LBDCF
TCBGT
CF
TCCF
TXFEC
F
IDLEC
F
ORECF NECF FECF PECF
www wwwwwwwwww
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 WUCF: Wake-up from low-power mode clear flag
Writing 1 to this bit clears the WUF flag in the USART_ISR register.
Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and
must be kept at reset value.
Refer to Section 35.4: USART implementation on
page 1116.
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CMCF: Character match clear flag
Writing 1 to this bit clears the CMF flag in the USART_ISR register.

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the STMicroelectronics STM32WL5 Series and is the answer not in the manual?

STMicroelectronics STM32WL5 Series Specifications

General IconGeneral
BrandSTMicroelectronics
ModelSTM32WL5 Series
CategoryMicrocontrollers
LanguageEnglish

Related product manuals