RM0453 Rev 5 1323/1450
RM0453 Debug support (DBG)
1435
38.4.3 DP control and status register (DP_CTRLSTATR)
Address offset: 0x04
and DP_SELECTR.DPBANKSEL = 0
Reset value: 0x0000 0000
Bit 3 WDERRCLR: write data error clear
0: No effect
1: Clears DP_CTRLSTATR.WDATAERR bit.
Bit 2 STKERRCLR: sticky error clear
0: No effect
1: Clears DP_CTRLSTATR.STICKYERR bit.
Bit 1 STKCMPCLR: sticky compare clear
0: No effect
1: Clears DP_CTRLSTATR.STICKYCMP bit
Bit 0 DAPABORT: data AP abort
Aborts current AP transaction if an excessive number of WAIT responses are returned,
indicating that the transaction is stalled.
0: No effect
1: Aborts the transaction.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res.
CDBG
PWRU
PACK
CDBG
PWRU
PREQ
Res. Res. Res. Res. TRNCNT[11:4]
rr rrrrrrrr
1514131211109876543210
TRNCNT[3:0] MASKLANE[3:0]
WDATA
ERR
READ
OK
STICK
YERR
STICK
YCMP
TRNMODE[1:0]
STICK
YORU
N
ORUN
DETEC
T
rrrrrrrrrrrc_w1rc_w1rrrc_w1r
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 CDBGPWRUPACK: see description in Section 38.3.7
0 = DAPCLK gated
1 = DAPCLK enabled
Bit 28 CDBGPWRUPREQ: control of DAPCLK enable request signal
0 = Requests DAPCLK gating
1 = Requests DAPCLK enabled
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:12 TRNCNT[11:0]: transaction counter
To program a sequence of transactions to incremental addresses via an AP, TRNCNT is
loaded with the number of transactions to perform. It is decremented at the successful
completion of each transaction.
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