RM0453 Rev 5 1325/1450
RM0453 Debug support (DBG)
1435
38.4.4 DP data link control register (DP_DLCR)
Address offset: 0x04
and DP_SELECTR.DPBANKSEL = 1
Reset value: 0x0000 0040
Bits 3:2 TRNMODE[1:0]: transfer mode for AP write operations
For read operations, this field must be set to 0x0.
0x0: Normal operation
– AP transactions are passed directly to the AP.
0x1: Pushed-verify operation
– The DP stores the write data and performs a read transaction at the target AP
address.
– The result of the read is compared with the stored data and if they do not match, the
STICKYCMP bit is set.
0x2: Pushed-compare operation
– The DP stores the write data and performs a read transaction at the target AP
address.
– The result of the read is compared with the stored data and if they match, the
STICKYCMP bit is set.
0x3: reserved
In pushed operation, only the data bytes indicated by the MASKLANE field are included in
the compare.
Bit 1 STICKYORUN: overrun (read only in SW-DP, R/W in JTAG-DP)
Indicates that an overrun occurred (new transaction received before previous transaction
completed). This bit is only set if the ORUNDETECT bit is set.
0: No overrun
1: An overrun occurred.
In SW-DP, STICKYORUN bit is read only, reset by writing 1 to the
DP_ABORTR.ORUNERRCLR bit.
In JTAG-DP, STICKYORUN bit is read, cleared by writing a 1 to it.
Bit 0 ORUNDETECT: overrun detection mode enable
0: Overrun detection disabled
1: Overrun detection enabled
In the event of an overrun, the STICKYORUN bit is set and subsequent transactions are
blocked until the STICKYORUN bit is cleared.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res.
TURNROUND
[1:0]
Res. Res. Res. Res. Res. Res. Res. Res.
rr
Bits 31:10 Reserved, must be kept at reset value.
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