Debug support (DBG) RM0453
1342/1450 RM0453 Rev 5
38.6.5 DWT sleep count register (DWT_SLPCNTR)
Address offset: 0x010
Reset value: 0x0000 0000
38.6.6 DWT LSU count register (DWT_LSUCNTR)
Address offset: 0x014
Reset value: 0x0000 0000
38.6.7 DWT fold count register (DWT_FOLDCNTR)
Address offset: 0x018
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. SLEEPCNT[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 SLEEPCNT[7:0]: sleep cycle counter
Counts the number of cycles spent in sleep mode (WFI, WFE, sleep-on-exit).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. LSUCNT[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 LSUCNT[7:0]: load store counter
Counts additional cycles required to execute load and store instructions.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. FOLDCNT[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 FOLDCNT[7:0]: folded instruction counter
Increments on each instruction that takes 0 cycles.
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