RM0453 Rev 5 1381/1450
RM0453 Debug support (DBG)
1435
38.9.4 FPB CoreSight peripheral identity register 4 (FPB_PIDR4)
Address offset: 0xFD0
Reset value: 0x0000 0004
Bits 31:30 REPLACE[1:0]: Defines the behavior when a match occurs between the COMP field and the
instruction fetch address.
0x0: reserved
0x1: Breakpoint on lower half-word, upper half-word is unaffected.
0x2: Breakpoint on upper half-word, lower half-word is unaffected.
0x3: Breakpoint on both upper and lower half-words
Bit 29 Reserved, must be kept at reset value.
Bits 28:2 COMP[26:0]: value to compare with address bits 28:2 of accesses to instruction code memory
(0x00000000 to 0x1FFFFFFF)
If a match occurs, the action to be taken is defined by the REPLACE field.
Bit 1 Reserved, must be kept at reset value.
Bit 0 ENABLE: comparator enable
The comparator is only enabled if both this bit and the FPB ENABLE bit in the FPB_CTRLR
register are set.
0: Disabled
1: Enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. F4KCOUNT[3:0] JEP106CON[3:0]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 F4KCOUNT[3:0]: register file size
0x0: Register file occupies a single 4-Kbyte region.
Bits 3:0 JEP106CON[3:0]: JEP106 continuation code
0x4: Arm
®
JEDEC code
To Next Page
Loading...
Need help?
General
