STMicroelectronics STM32WL5 Series - Page 1393

RM0453 Rev 5 1393/1450
RM0453 Debug support (DBG)
1435
38.10.11 ITM CoreSight peripheral identity register 1 (ITM_CIDR1)
Address offset: 0xFF4
Reset value: 0x0000 00E0
38.10.12 ITM CoreSight component identity register 2 (ITM_CIDR2)
Address offset: 0xFF8
Reset value: 0x0000 0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 CLASS[3:0]: component ID bits [15:12] - component class
0xE: Trace generator component
Bits 3:0 PREAMBLE[11:8]: component ID bits [11:8]
0x0: Common ID value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[19:12]: component ID bits [23:16]
0x05: Common ID value