Debug support (DBG) RM0453
1408/1450 RM0453 Rev 5
38.12.1 DBGMCU identity code register (DBGMCU_IDCODER)
Address offset: 0x000
Reset value: 0xXXXX 6497
38.12.2 DBGMCU configuration register (DBGMCU_CR)
Address offset: 0x004
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID[15:0]
rrrrrr r r r r rrrrrr
1514131211109876543210
Res. Res. Res. Res. DEV_ID[11:0]
rrrrrrrrrrrr
Bits 31:16 REV_ID[15:0]: revision
For values, refer to the device errata sheet.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DEV_ID[11:0]: device ID
0x497: STM32WL5x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_
STANDBY
DBG_
STOP
DBG_
SLEEP
rw rw rw
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 DBG_STANDBY: Allows debug in Standby mode
This bit does not influence CPU2 operation, CPU2 cannot be debugged in Standby mode
even when this bit is enabled.
0: Normal operation. All clocks are disabled and the domain powered down automatically in
Standby mode.
1: Automatic clock stop/power down disabled. All active clocks and oscillators continue to run
during Standby mode and the domain supply is maintained, allowing full debug capability. On
exit from Standby mode, a domain reset is performed.
Bit 1 DBG_STOP: Allows debug in Stop mode
This bit does not influence CPU2 operation, CPU2 cannot be debugged in Stop mode even
when this bit is enabled.
0: Normal operation. All clocks are disabled automatically in Stop mode.
1: Automatic clock stop disabled. All active clocks and oscillators continue to run during Stop
mode, allowing full debug capability. On exit from Stop mode, the clock settings are set to the
Stop mode exit state.
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