STMicroelectronics STM32WL5 Series - Page 1424

Debug support (DBG) RM0453
1424/1450 RM0453 Rev 5
38.13.16 CPU2 ROM2 CoreSight peripheral identity register 2
(C2ROM2_PIDR2)
Address offset: 0xFE8
Reset value: 0x0000 000B
38.13.17 CPU2 ROM2 CoreSight peripheral identity register 3
(C2ROM2_PIDR3)
Address offset: 0xFEC
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. REVISION[3:0] JEDEC JEP106ID[6:4]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 REVISION[3:0]: component revision number
0x0: rev r0p0
Bit 3 JEDEC: JEDEC assigned value
1: Designer ID specified by JEDEC
Bits 2:0 JEP106ID[6:4]: JEP106 identity code bits [6:4]
0x3: Arm
®
JEDEC code
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. REVAND[3:0] CMOD[3:0]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 REVAND[3:0]: metal fix version
0x0: No metal fix
Bits 3:0 CMOD[3:0]: customer modified
0x0: No customer modifications