STMicroelectronics STM32WL5 Series User Manual

Revision history RM0453
1442/1450 RM0453 Rev 5
19-Apr-2022 3
Updated:
– Section 4.3.1: Flash memory organization
– Section 5.1: Sub-GHz radio introduction
– Section 5.2: Sub-GHz radio main features
– Section 5.5.3: FSK modem
– Figure 13: Generic packet frames format
– Section 5.5.7: BPSK framing
– Table 36: Recommended CAD configuration settings
– LoRa Set_LoRaSymbTimeout() command
– Get_RxBufferStatus() command
– New registers in Section 5.10: Sub-GHz radio registers
– SMPSEN desc in Section 6.6.8: PWR control register 5 (PWR_CR5)
– Section 18.3.3: Calibration (ADCAL)
– Section 18.3.7: Configuring the ADC
– Notes in Section 18.12.4: ADC configuration register 1 (ADC_CFGR1) and
Section 18.12.5: ADC configuration register 2 (ADC_CFGR2)
– Health checks
– Section 22.3.4: RNG initialization
– Section 22.5: RNG processing time
– Section 22.6.2: Validation conditions
– RNDATA desc in Section 22.7.3: RNG data register (RNG_DR)
– Section 23.4.16: AES DMA interface
– Note in Section 25.3.16: Using the break function
– Section 25.4.4: TIM1 DMA/interrupt enable register (TIM1_DIER)
– Note in Section 27.3.12: Bidirectional break inputs
– Section 27.3.13: 6-step PWM generation
– Note on Section 32.6.1: RTC time register (RTC_TR)
–New Section 40: Important security notice
16-Nov-2022 4
Updated:
– Table 31: Sub-GHz radio transmit high output power
– Table 35: LoRa bandwidth setting
– Table 39: PA optimal setting and operating modes
– Register names from Section 5.13.69 to Section 5.13.76: Sub-GHz radio generic
synchronization word control register 7 (SUBGHZ_GSYNCR7)
– Address offset of Section 5.13.167: Sub-GHz radio AGC RSSI control register
(SUBGHZ_AGCRSSICTL0R)
–New Section 5.13.238: Sub-GHz radio regulator drive control register
(SUBGHZ_REGDRVCR)
– RFEOLF description in Section 6.6.6: Power status register 2 (PWR_SR2)
– SVCall description in Table 91: CPU1 vVector table
– HSEM description in Table 92: CPU2 vector table
– DAC_DHR8RD, DAC_DHR12RD, and DAC_DHR12LD registers removed
in Section 19: Digital-to-analog converter (DAC)
12-Jan-2023 5
Updated Section 7.2: Clocks, Section 7.2.12: SPI2S2 clock, Section 38.10.2: ITM trace
enable register (ITM_TER), and Section 38.10.3: ITM trace privilege register (ITM_TPR).
Minor text edits across the whole document.
Table 288. Document revision history (continued)
Date Revision Changes

STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English