Embedded flash memory (FLASH) RM0453
148/1450 RM0453 Rev 5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res.
RDERRIE
ERRIE EOPIE Res. Res. Res. Res. Res. FSTPG Res. STRT
rw rw rw rw rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. PNB[6:0] MER PER PG
rw rw rw rw rw rw rw rw rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 RDERRIE: PCROP read error interrupt enable
This bit enables the interrupt generation when RDERR in FLASH_SR is set to 1.
0: PCROP read error interrupt disabled
1: PCROP read error interrupt enabled
Bit 25 ERRIE: error interrupt enable
This bit enables the interrupt generation when OPERR in FLASH_SR is set to 1.
0: OPERR error interrupt disabled
1: OPERR error interrupt enabled
Bit 24 EOPIE: end of operation interrupt enable
This bit enables the interrupt generation when EOP in FLASH_SR is set to 1.
0: EOP Interrupt disabled
1: EOP Interrupt enabled
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 FSTPG: fast programming
0: Fast programming disabled
1: Fast programming enabled
Bit 17 Reserved, must be kept at reset value.
Bit 16 STRT: start
When set, this bit triggers an erase operation. If MER and PER bits are reset and the STRT
bit is set, an unpredictable behavior may occur without generating any error flag. This
condition is forbidden.
This bit is set only by software and is cleared when BSY is cleared in FLASH_SR.
When the system is secure (ESE = 1) starting operations by the CPU1, involving secure
flash pages is rejected and a bus error is generated.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:3 PNB[6:0]: page number selection
These bits select the 2-Kbyte page to erase.
0x00: page 0
0x01: page 1
...
0x7F: page 127
Bit 2 MER: mass erase
This bit triggers the mass erase (all user pages) when set.
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