STMicroelectronics STM32WL5 Series - Page 198

Sub-GHz radio (SUBGHZ) RM0453
198/1450 RM0453 Rev 5
Cfg_DioIrq() command
Cfg_DioIrq(IrqMask, Irq1Mask, Irq2Mask, Irq3Mask) allows interrupts to be
masked and mapped on the IRQ lines.
Get_IrqStatus() command
Get_IrqStatus(Status, IrqStatus) returns the IRQ status.
7 CadDone Channel activity detection finished LoRa Cad
8 CadDetected Channel activity detected LoRa Cad
9 Timeout RX or TX timeout LoRa and GFSK Rx and Tx
15:10 Not applicable Reserved Not applicable
Table 37. IRQ bit mapping and definition (continued)
Bit Source Description Packet type Operation
012345678
Opcode IrqMask[15:0] Irq1Mask[15:0]Irq2Mask[15:0]Irq3Mask[15:0]
wwwwwwwww
byte 0 bits 7:0 Opcode: 0x08
bytes 2:1 bits 15:0 IrqMask[15:0]: Global interrupt enable
See Table 37 for interrupt bit map definition. For each bit:
0: IRQ disabled
1: IRQ enabled
bytes 4:3 bits 15:0 Irq1Mask[15:0]: IRQ1 line Interrupt enable
0: interrupt on IRQ1 line disable
1: interrupt on IRQ1 line enabled
bytes 6:5 bits 15:0 Irq2Mask[15:0]: IRQ2 line Interrupt enable
0: interrupt on IRQ2 line disable
1: interrupt on IRQ2 line enabled
bytes 8:7 bits 15:0 Irq3Mask[15:0]: IRQ3 line Interrupt enable
0: interrupt on IRQ3 line disable
1: interrupt on IRQ3 line enabled
0123
Opcode Status[7:0] IrqStatus[15:0]
wrrr
byte 0 bits 7:0 Opcode: 0x12
byte 1 bits 7:0 Status[7:0]: see Get_Status() command
bytes 3:2 bits 15:0 IrqStatus[15:0]: interrupt pending status information
See Table 37 for interrupt bit map definition. For each bit:
0: IRQ not pending
1: IRQ pending