RM0453 Rev 5 321/1450
RM0453 Reset and clock control (RCC)
371
7.4.8 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
Address offset: 0x028
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
7.4.9 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
Address offset: 0x02C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 76543210
Res. Res. Res.
CRC
RST
Res. Res. Res. Res. Res. Res. Res. Res. Res.
DMA
MUX1
RST
DMA2
RST
DMA1
RST
rw rw rw rw
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
This bit is set and cleared by software.
0: No effect
1: CRC reset
Bits 11:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1RST: DMAMUX1 reset
This bit is set and cleared by software.
0: No effect
1: DMAMUX1 reset
Bit 1 DMA2RST: DMA2 reset
This bit is set and cleared by software.
0: No effect
1: DMA2 reset
Bit 0 DMA1RST: DMA1 reset
This bit is set and cleared by software.
0: No effect
1: DMA1 reset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 76543210
Res. Res. Res. Res. Res. Res. Res. Res.
GPIOH
RST
Res. Res. Res. Res.
GPIOC
RST
GPIOB
RST
GPIOA
RST
rw rw rw rw
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