Reset and clock control (RCC) RM0453
326/1450 RM0453 Rev 5
7.4.14 RCC APB3 peripheral reset register (RCC_APB3RSTR)
Address offset: 0x044
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bit 12 SPI1RST: SPI1 reset
This bit is set and cleared by software.
0: No effect
1: SPI1 reset
Bit 11 TIM1RST: Timer 1 reset
This bit is set and cleared by software.
0: No effect
1: TIM1 reset
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCRST: ADC reset
This bit is set and cleared by software.
0: No effect
1: ADC reset
Bits 8:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SUBGHZSPIRST
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SUBGHZSPIRST: Sub-GHz radio SPI reset
This bit is set and cleared by software.
0: No effect
1: Sub-GHz radio SPI reset
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