RM0453 Rev 5 351/1450
RM0453 Reset and clock control (RCC)
371
7.4.33 RCC CPU2 AHB1 peripheral clock enable register
(RCC_C2AHB1ENR)
Address offset: 0x148
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access from
CPU2 is not supported.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res.
CRC
EN
Res. Res. Res. Res. Res. Res. Res. Res. Res.
DMA
MUX1
EN
DMA2
EN
DMA1
EN
rw rw rw rw
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CPU2 CRC clock enable
This bit is set and cleared by software.
0: CRC clock disabled for CPU2
1: CRC clock enabled for CPU2
Bits 11:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1EN: CPU2 DMAMUX1 clock enable
This bit is set and cleared by software.
0: DMAMUX1 clock disabled for CPU2
1: DMAMUX1 clock enabled for CPU2
Bit 1 DMA2EN: CPU2 DMA2 clock enable
This bit is set and cleared by software.
0: DMA2 clock disabled for CPU2
1: DMA2 clock enabled for CPU2
Bit 0 DMA1EN: CPU2 DMA1 clock enable
This bit is set and cleared by software.
0: DMA1 clock disabled for CPU2
1: DMA1 clock enabled for CPU2
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