Hardware semaphore (HSEM) RM0453
372/1450 RM0453 Rev 5
8 Hardware semaphore (HSEM)
8.1 Introduction
The hardware semaphore block provides 16 (32-bit) register based semaphores.
The semaphores can be used to ensure synchronization between different processes
running between different cores. The HSEM provides a non-blocking mechanism to lock
semaphores in an atomic way. The following functions are provided:
• Semaphore lock, in two ways:
– 2-step lock: by writing COREID and PROCID to the semaphore, followed by a
read check
– 1-step lock: by reading the COREID from the semaphore
• Interrupt generation when a semaphore is unlocked
– Each semaphore may generate an interrupt on one of the interrupt lines
• Semaphore clear protection
– A semaphore is only unlocked when COREID and PROCID match
• Global semaphore clear per COREID
8.2 Main features
The HSEM includes the following features:
• 16 (32-bit) semaphores
• 8-bit PROCID
• 4-bit COREID
• One interrupt line per processor
• Lock indication
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