STMicroelectronics STM32WL5 Series - Page 383

RM0453 Rev 5 383/1450
RM0453 Hardware semaphore (HSEM)
385
8.4.8 HSEM clear semaphore key register (HSEM_KEYR)
Address offset: 0x144
Reset value: 0x0000 0000
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 Reserved, must be kept at reset value.
Bits 11:8 COREID[3:0]: COREID of semaphores to be cleared
This field can be written by software and is always read 0.
This field indicates the COREID for which the semaphores are cleared when writing the
HSEM_CR.
Bits 7:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Bits 31:16 KEY[15:0]: Semaphore clear key
This field can be written and read by software.
Key value to match when clearing semaphores.
Bits 15:0 Reserved, must be kept at reset value.