RM0453 Rev 5 393/1450
RM0453 Inter-processor communication controller (IPCC)
399
To receive the response the channel free interrupt is unmasked (CHnFM = 0):
• On a TX free interrupt, the sending processor checks which channel became free,
masks the associated channel free interrupt (CHnFM) and reads the response from the
memory.
• Once the complete response is retrieved, the response pending software variable is
cleared. The channel status is not changed, access to the memory is kept to post the
subsequent communication data.
9.3.4 IPCC interrupts
There are four interrupt lines :
• two RX channel occupied interrupts, one for each processor:
– Interrupt enable RXOIE per processor
– Individual mask CHnOM per channel
• two TX channel free interrupts, one for each processor
– Interrupt enable TXFIE per processor
– Individual mask CHnFM per channel
The RX occupied interrupt is used by the receiving processor and indicates when an
unmasked channel status indicates occupied (CHnF = 1).
The TX free interrupt is used by the sending processor, and indicates when an unmasked
channel status indicates free (CHnF = 0).
A secure channel only generates a secure interrupt, and only in the case when the channel
is secure unmasked and global secure enabled.
A non-secure channel only generates a non-secure interrupt, and only in the case when the
channel is non-secure unmasked and global non-secure enabled.
9.4 IPCC registers
The peripheral registers must be accessed by words (32-bit). Byte (8-bit) and half-word
(16-bit) accesses are not permitted and do not generate a bus error.
9.4.1 IPCC processor 1 control register (IPCC_C1CR)
Address offset: 0x000
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TXFIE
rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RXOIE
rw
Bits 31:17 Reserved, must be kept at reset value.
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