Inter-processor communication controller (IPCC) RM0453
396/1450 RM0453 Rev 5
9.4.5 IPCC processor 2 control register (IPCC_C2CR)
Address offset: 0x010
Reset value: 0x0000 0000
9.4.6 IPCC processor 2 mask register (IPCC_C2MR)
Address offset: 0x014
Reset value: 0xFFFF FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TXFIE
rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RXOIE
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 TXFIE: Processor 2 transmit channel free interrupt enable
Associated with IPCC_C2TOC1SR.
1: Enable an unmasked processor 2 transmit channel free to generate a TX free interrupt.
0: Processor 2 TX free interrupt disabled
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 RXOIE: Processor 2 receive channel occupied interrupt enable
Associated with IPCC_C1TOC2SR.
1: Enable an unmasked processor 2 receive channel occupied to generate an RX occupied
interrupt.
0: Processor 2 RX occupied interrupt disabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CH6
FM
CH5
FM
CH4
FM
CH3
FM
CH2
FM
CH1
FM
rw rw rw rw rw rw
15141312111098765 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CH6
OM
CH5
OM
CH4
OM
CH3
OM
CH2
OM
CH1
OM
rw rw rw rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:16 CHnFM: Processor 2 transmit channel n free interrupt mask (n = 6 to 1).
Associated with IPCC_C2TOC1SR.CHnF
1: Transmit channel n free interrupt masked.
0: Transmit channel n free interrupt not masked.
Bits 15:6 Reserved, must be kept at reset value.
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