RM0453 Rev 5 415/1450
RM0453 General-purpose I/Os (GPIO)
431
10.4.11 GPIOx bit reset register (GPIOx_BRR) (x = A to B)
Address offset: Block A: 0x0028
Address offset: Block B: 0x0428
Reset value: 0x0000 0000
10.4.12 GPIOC mode register (GPIOC_MODER)
Address offset: 0x0800
Reset value: 0xFC00 3FFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 BRy: Port Pxy reset output data bit [15:0] in GPIOx_ODR (y = 15 to 0)
These bits are read clear-write 1. A read to these bits returns the value 0x0000.
0: No action on the corresponding GPIOx_ODR.OD[y] bit
1: Resets the corresponding GPIOx_ODR.OD[y] bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE15[1:0] MODE14[1:0] MODE13[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw
1514131211109876543210
Res. Res. MODE6[1:0] MODE5[1:0] MODE4[1:0] MODE3[1:0] MODE2[1:0] MODE1[1:0] MODE0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 MODE15[1:0]: Port PC15 IO type configuration
Bits 29:28 MODE14[1:0]: Port PC14 IO type configuration
Bits 27:26 MODE13[1:0]: Port PC13 IO type configuration
Bits 25:14 Reserved, must be kept at reset value.
Bits 13:12 MODE6[1:0]: Port PC6 IO type configuration
Bits 11:10 MODE5[1:0]: Port PC5 IO type configuration
Bits 9:8 MODE4[1:0]: Port PC4 IO type configuration
Bits 7:6 MODE3[1:0]: Port PC3 IO type configuration
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