General-purpose I/Os (GPIO) RM0453
422/1450 RM0453 Rev 5
10.4.22 GPIOC bit reset register (GPIOC_BRR)
Address offset: 0x0828
Reset value: 0x0000 0000
10.4.23 GPIOH mode register (GPIOH_MODER)
Address offset: 0x1C00
Reset value: 0x0000 00C0
Bits 23:20 AFSEL13[3:0]: Port PC13 alternate function selection
These bits are written by software to configure alternate function I/Os.
0x0: AF0 selected
0x1: AF1 selected
0x2: AF2 selected
...
0xE: AF14 selected
0xF: AF15 selected
Bits 19:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
BR15 BR14 BR13 Res. Res. Res. Res. Res. Res. BR6 BR5 BR4 BR3 BR2 BR1 BR0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:13 BRy: Port PCy reset output data bit [15] in GPIOC_ODR (y = 15 to 13)
These bits are read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOC_ODR.OD0
1: Resets the corresponding GPIOC_ODR.OD0.
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 BRy: Port PCy reset output data bit [6] in GPIOC_ODR (y = 6 to 0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. MODE3[1:0] Res. Res. Res. Res. Res. Res.
rw rw
Bits 31:8 Reserved, must be kept at reset value.
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