STMicroelectronics STM32WL5 Series User Manual

RM0453 Rev 5 443/1450
RM0453 System configuration controller (SYSCFG)
445
11.2.14 SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2)
Address offset: 0x10C
Reset value: 0x0000 0000
11.2.15 SYSCFG radio debug control register (SYSCFG_RFDCR)
Address offset: 0x208
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PVDIM Res.
PVM3I
M
Res. Res.
rw rw
1514131211109876543210
DMAM
UX1IM
DMA2C
H7IM
DMA2C
H6IM
DMA2C
H5IM
DMA2C
H4IM
DMA2C
H3IM
DMA2C
H2IM
DMA2C
H1IM
Res.
DMA1C
H7IM
DMA1C
H6IM
DMA1C
H5IM
DMA1C
H4IM
DMA1C
H3IM
DMA1C
H2IM
DMA1C
H1IM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 PVDIM: PVD interrupt mask to CPU2
0: PVD interrupt forwarded to CPU2
1. PVD interrupt to CPU2 masked
Bit 19 Reserved, must be kept at reset value.
Bit 18 PVM3IM: PVM3 interrupt mask to CPU2
0: PVM3 interrupt forwarded to CPU2
1. PVM3 interrupt to CPU2 masked.
Bits 17:16 Reserved, must be kept at reset value.
Bit 15 DMAMUX1IM: DMAMUX1 interrupt mask to CPU2
0: DMAMUX1 interrupt forwarded to CPU2
1. DMAMUX1 interrupt to CPU2 masked
Bits 14:8 DMA2CHxIM: DMA2CHx interrupt mask to CPU2 (x = 7 to 1)
0: DMA2CHx interrupt forwarded to CPU2
1. DMA2CHx interrupt to CPU2 masked
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 DMA1CHxIM: DMA1CHx interrupt mask to CPU2 (x = 7 to 1)
0: DMA1CHx interrupt forwarded to CPU2
1. DMA1CHx interrupt to CPU2 masked
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RFTBS
EL
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STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English