RM0453 Rev 5 461/1450
RM0453 Direct memory access controller (DMA)
479
When a channel is configured in a privileged (or unprivileged) mode, the AHB master
transfers from the source and to the destination, are privileged (respectively unprivileged).
DMA generates a privileged bus, dma_priv[7:0], reflecting the PRIV bit of the DMA_CCRx
register, in order to keep the other hardware peripherals, like DMAMUX, informed of the
privileged / unprivileged state of each DMA channel x.
The DMA controller also generates a privileged illegal access pulse event on an illegal non-
privileged software access to a privileged DMA register or register field. This event is ORed
with the secure illegal pulse access event in order to generate an illegal access pulse event,
dma_ilac, which is routed to the secure interrupt controller.
Channel configuration procedure
The following sequence is needed to configure a DMA channel x:
1. Set a channel x to secure or non-secure, by a secure write access to the secure SECM
bit of the DMA_CCRx register. Set a channel x to privileged or unprivileged, by a
privileged write access to the privileged PRIV bit of the DMA_CCRx register.
2. Set the peripheral register address in the DMA_CPARx register.
The data is moved from/to this address to/from the memory after the peripheral event,
or after the channel is enabled in memory-to-memory mode.
3. Set the memory address in the DMA_CMARx register.
The data is written to/read from the memory after the peripheral event or after the
channel is enabled in memory-to-memory mode.
4. Configure the total number of data to transfer in the DMA_CNDTRx register.
After each data transfer, this value is decremented.
5. Configure the parameters listed below in the DMA_CCRx register:
– the channel priority
– the data transfer direction
– the security level of the data transfers from source and to destination when the
channel is secure
– the circular mode
– the peripheral and memory incremented mode
– the peripheral and memory data size
– the interrupt enable at half and/or full transfer and/or transfer error
6. Activate the channel by setting the EN bit in the DMA_CCRx register.
A channel, as soon as enabled, may serve any DMA request from the peripheral connected
to this channel, or may start a memory-to-memory block transfer.
Note: The two last steps of the channel configuration procedure may be merged into a single
access to the DMA_CCRx register, to configure and enable the channel.
Channel state and disabling a channel
A channel x in active state is an enabled channel (read DMA_CCRx.EN = 1). An active
channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set
to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0). In case there is a
transfer error, the channel is automatically disabled by hardware (DMA_CCRx.EN = 0).
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