RM0453 Rev 5 475/1450
RM0453 Direct memory access controller (DMA)
479
13.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)
Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
Bit 2 HTIE: Half transfer interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 1 TCIE: Transfer complete interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 0 EN: Channel enable
When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again
by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by
setting the CTEIFx bit of the DMA_IFCR register).
0: Disabled
1: Enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. NDT[17:16]
rw rw
1514131211109876543210
NDT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:0 NDT[17:0]: Number of data to transfer (0 to 2
18
- 1)
This bitfield is updated by hardware when the channel is enabled:
– It is decremented after each single DMA ‘read followed by write’ transfer, indicating
the remaining amount of data items to transfer.
– It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
– It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not).
Note: This bitfield is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
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