Extended interrupts and event controller (EXTI) RM0453
518/1450 RM0453 Rev 5
16.6.5 EXTI rising trigger selection register (EXTI_RTSR2)
Address offset: 0x020
Reset value: 0x0000 0000
Contains only register bits for configurable events.
16.6.6 EXTI falling trigger selection register (EXTI_FTSR2)
Address offset: 0x024
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. RT45 Res. Res. Res. RT41 RT40 Res. Res. Res. Res. Res. RT34 Res. Res.
rw rw rw rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 RT45: rising trigger event configuration bit of configurable event input 45
0: Rising trigger disabled (for event and interrupt) for input line
1: Rising trigger enabled (for event and interrupt) for input line
Note: The configurable event inputs are edge triggered. No glitch must be generated on
these inputs. If a rising edge on the configurable event input occurs while writing to the
register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this
case, both edges generate a trigger.
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 RT41: rising trigger event configuration bit of configurable event input 41
Bit 8 RT40: rising trigger event configuration bit of configurable event input 40
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 RT34: rising trigger event configuration bit of configurable event input 34
Bits 1:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. FT45 Res. Res. Res. FT41 FT40 Res. Res. Res. Res. Res. FT34 Res. Res.
rw rw rw rw
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