Extended interrupts and event controller (EXTI) RM0453
520/1450 RM0453 Rev 5
16.6.8 EXTI pending register (EXTI_PR2)
Address offset: 0x02C
Reset value: 0x0000 0000
Contains only register bits for configurable events.
16.6.9 EXTI interrupt mask register (EXTI_CnIMR1)
Address offset: Block 1: 0x080
Address offset: Block 2: 0x0C0
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. PIF45 Res. Res. Res. PIF41 PIF40 Res. Res. Res. Res. Res. PIF34 Res. Res.
rw rw rw rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PIF45: pending bit on event input 45
These bits are set when the selected edge event or an EXTI_SWIER software trigger arrives
on the configurable event line. This bit is cleared by writing 1 to it.
0: No trigger request occurred.
1: Trigger request occurred.
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 PIF41: pending bit on event input 41
Bit 8 PIF40: pending bit on event input 40
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PIF34: pending bit on event input 34
Bits 1:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
IM[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 IM[31:0]: Wake-up with interrupt mask on event input x (x= 31 to 0)
For each bit of this field:
0: Wake-up with interrupt request from line x is masked.
1: Wake-up with Interrupt request from line x is unmasked.
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