Analog-to-digital converter (ADC) RM0453
578/1450 RM0453 Rev 5
Bits 8:6 EXTSEL[2:0]: External trigger selection
These bits select the external event used to trigger the start of conversion (refer to Table 102:
External triggers for details):
000: TRG0
001: TRG1
010: TRG2
011: TRG3
100: TRG4
101: TRG5
110: TRG6
111: TRG7
Note:
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Figure 71:
Data alignment and resolution (oversampling disabled: OVSE = 0) on page 552
0: Right alignment
1: Left alignment
Note:
Bits 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12 bits
01: 10 bits
10: 8 bits
11: 6 bits
Bit 2 SCANDIR: Scan sequence direction
This bit is set and cleared by software to select the direction in which the channels is scanned
in the sequence. It is effective only if CHSELMOD bit is cleared.
0: Upward scan (from CHSEL0 to CHSEL17)
1: Backward scan (from CHSEL17 to CHSEL0)
Note:
If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register
or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN = 1.
0: DMA one shot mode selected
1: DMA circular mode selected
For more details, refer to Section 18.5.5: Managing converted data using the DMA on
page 554
Note:
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows
the DMA controller to be used to manage automatically the converted data. For more details,
refer to Section 18.5.5: Managing converted data using the DMA on page 554.
0: DMA disabled
1: DMA enabled
Note:
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